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Hardware register
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#	Item
31	ALINT™ Design Rule Checking Methodology Detects Design Flaws Early Aldec’s ALINT™ design analysis tool identifies critical design Add to Reading List Source URL: www.aldec.com Language: English - Date: 2014-09-11 15:01:15 Integrated circuits Aldec Electronic design VHDL Verilog Field-programmable gate array Application-specific integrated circuit Integrated circuit design Register-transfer level Electronic engineering Electronic design automation Hardware description languages
32	Microsoft Word - IHD_OS_Vol1_Part2.doc Add to Reading List Source URL: 01.org Language: English - Date: 2014-07-09 14:03:35 Computer memory Central processing unit GTT Graphics address remapping table Page table Control register Intel Memory address Computer hardware Computing Virtual memory
33	PDF Document Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:32:04 Central processing unit CPU cache Processor register Multithreading Cache Cell Thread Parallel computing Multi-core processor Computer architecture Computer hardware Computing
34	D Intel® XScale™ Microarchitecture Technical Summary Product Features Add to Reading List Source URL: www.a4com.de Language: English - Date: 2006-12-21 09:47:13 Computing ARM architecture XScale Control register CPU cache Microarchitecture Instruction set Processor register Comparison of CPU architectures Computer architecture Computer hardware Central processing unit
35	Today’s Big Idea CS252 Graduate Computer Architecture Lecture 18: Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:51 Central processing unit Branch predictor Instruction set architectures Alpha 21264 Register renaming DEC Alpha CPU cache Out-of-order execution Re-order buffer Computer architecture Computer hardware Computer engineering
36	Discovering Nontrivial and Functional Behavior in Register Machines Add to Reading List Source URL: www.complex-systems.com Language: English - Date: 2013-09-03 11:08:27 Computing Computer hardware Register machine Program counter Instruction set Processor register Stack machine Random access machine Models of computation Central processing unit Computer architecture
37	Federal Register / Vol. 80, NoTuesday, March 17, Notices factor hardware token authentication. Non-electronic records are secured in Add to Reading List Source URL: science.nasa.gov Language: English - Date: 2015-04-06 14:29:24 Government Government of the United States NASA National Science Board
38	Microsoft Word - SSD1926-application_note-register_table_1.0.doc Add to Reading List Source URL: www.solomon-systech.com Language: English - Date: 2013-02-25 01:23:31 Electronic engineering Computer hardware Extended display identification data Electronics TI MSP430 Intel Color depth Microcontrollers
39	Late-Binding: Enabling Unordered Load-Store Queues Franziska Roesner x Simha Sethumadhavan x y x Joel S. Emer Add to Reading List Source URL: www.franziroesner.com Language: English - Date: 2009-10-21 14:03:34 Central processing unit Memory disambiguation CPU cache Microarchitecture Hazard Branch predictor Processor register Out-of-order execution DEC Alpha Computer architecture Computer hardware Computer engineering
40	Analysis of various scalar, vector, and parallel implementations of RandomAccess∗ Piotr Luszczek Jack Dongarra Add to Reading List Source URL: icl.cs.utk.edu Language: English - Date: 2010-06-17 21:10:41 Computing Computer hardware Linear congruential generator Random number generation CPU cache Pseudo-ring Trie Pseudorandom number generators Mathematics Linear feedback shift register

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